Generally, an IC device may include a variety of components such as transistors, capacitors, inductors, voltage regulators, resistors, or the like, which may provide various functionalities in operation of an IC device. With industry demand for more efficient, smaller sized, and multifunctioning IC devices, manufacturing of such devices requires advanced IC design and manufacturing processes. Two coupled inductors have been used for ripple cancelation in integrated voltage regulators (IVRs). With a special timing scheme, the two phases perform complete current ripple cancellation across all duty cycles in the output. Moreover, the ripple current through each inductor is substantially reduced by a factor of (1+k) which decreases the inductor loss and improves the power supply efficiency. This converter topology enables the use of ultra-small inductors (2 nH) in a high efficiency converter and an ultra-small capacitor (2 nF) in an ultra-compact size. Components, such as an inductor without a core, may be challenging to implement in an IC device, wherein a thicker (e.g., 2 μm) metal layer may be required for forming the inductor coil/spiral. Coupled inductors may be implemented in a single metal layer (e.g., side-by-side) or in multiple adjacent (e.g., stacked) metal layers; however, in either case, the implementation would require a layout area in one or more layers, which may already include congested and compacted layouts of other components.
FIG. 1A schematically illustrates an example of coupled inductors implemented on a same layer in an IC device. Substrate layer 101 includes a coupled inductor coils/spirals 103 and 105 that are implemented on the same layer. As mentioned, such an implementation may require large and sufficient layout area to form the multiple turns in the coils 103 and 105 for sufficient inductance (e.g. 1 to 10 μH) and performance. Also, a coupling coefficient between the two inductors may be low since only a portion of the magnetic flux from one inductor can be picked up by the other. Additionally, thickness limitations of metal layers in the IC device may adversely impact functionality (e.g., current carrying capacity) of the inductors in a component (e.g., a voltage regulator) employing them.
Similar issues are associated with another example of coupled inductors as illustrated in FIG. 1B, where inductor coils 107 and 109 are implemented on two different layers 101a and 101b, respectively. This implementation still requires precious die area in the IC device and lots of turns of the coils for sufficient inductance. Additionally, the coils would need to be formed in two adjacent metal layers that have the same thickness; however, some of the metal layers (e.g., top and lower) may have different thicknesses (for example the top metal layer is typically much thicker), which can impact functionality and performance quality of the inductors as well as the component(s) utilizing such inductors. In other IC design and fabrication methods, inductors may be implemented by creating deep trenches (e.g. 100 μm deep) in a silicon interposer for the coils and filling with copper, but more complex fabrication processes would be necessary. Further, although the inductor area may be small (e.g., 0.8×0.4 mm2), and spacing between inductors is not critical, there is an additional silicon wafer cost.
Therefore, there is a need for a methodology enabling formation of coupled inductors in an IC device with a reduced area without metal and silicon thickness issues and resulting devices.